1. Field of the Invention
The present invention relates to a capacitor of a semiconductor device and a method of fabricating the same, and more particularly, to a DRAM cell capacitor applicable to a highly integrated device and a method of fabricating the capacitor.
2. Description of the Related Art
As the degree of integration of semiconductor devices increases, the sizes of cells are reduced and the effective areas of lower electrodes in cell capacitors are also reduced in semiconductor devices such as DRAMs. However, in order to maintain stable operation of a semiconductor device, cell capacitance greater than a predetermined value must be sustained. In order to ensure high cell capacitance in a narrow area, a high-k dielectric layer formed of a material with a larger dielectric constant than a capacitor dielectric layer such as a silicon oxide layer, a silicon nitride layer, or a silicon nitride layer/silicon oxide layer is required. For example, a high-k dielectric layer such as a tantalum oxide layer (Ta2O5, dielectric constant: 20˜60), a hafnium oxide layer (HfO2, dielectric constant: ˜20), a titanium oxide layer (TiO2, dielectric constant: ˜40), an aluminum oxide layer (Al2O3, dielectric constant: ˜10), or a lanthanum oxide layer (La2O3, dielectric constant: ˜40) can be used as the dielectric layer.
However, doped polysilicon, which is conventionally used for a capacitor's upper and lower electrodes, interacts with high-k dielectric layers, and thus degrades the electrical characteristics of the capacitor. In addition, since the doped polysilicon has a small work function, the barrier height formed between the high-k dielectric layer, which has a large work function, and the doped polysilicon dielectric layer is relatively low. If this barrier is not high enough, electrons tunnel between the upper and lower electrodes, thus increasing leakage current. In addition, when the doped polysilicon is used as the electrode, the doped polysilicon layer should be formed or heat-treated at a temperature of 600° C. or higher in order to activate the dopant of the doped polysilicon electrode. However, a high temperature process such as this may additionally result in a higher leakage current of the capacitor.
Instead of a conventional semiconductor-insulator-semiconductor (SIS) capacitor using the doped polysilicon electrode as the upper and lower electrodes, it has been suggested that a metal layer, having less reactivity than the polysilicon layer, be used as the upper electrode of a capacitor employing a high-k dielectric layer, or as both the upper and lower electrodes of such a capacitor. The former is called a metal-insulator-semiconductor (MIS) capacitor, and the latter is called a metal-insulator-metal (MIM) capacitor.
However, when the upper electrode is formed of only the metal layer, wet etching, dry etching, and stress related problems are generated during an integration process, and the metal layer cannot perform as a resistor layer for delaying signals since the layer has small resistivity. Therefore, a dual-layer, in which a doped polysilicon layer is stacked on a metal layer (e.g., a TiN layer), is used as the upper electrode. Here, the doped polysilicon layer is formed by depositing amorphous silicon using a low pressure chemical vapor deposition (LPCVD) method at a temperature of about 430-550° C., and then performing an activation heat treatment on the deposited amorphous silicon at a high temperature of 600° C. or higher for 30 minutes or longer. The resulting upper electrode may have a more appropriate resistance. In a semiconductor device, if the resistance of the upper electrode is large, the resistance may function as signal noise. However, due to the heat treatment of the doped polysilicon layer, the leakage current of the dual layer electrode may be higher than the leakage current of an electrode using only the metal layer.
Therefore, it is desirable to obtain an electrode material used in an upper electrode of a capacitor which is capable of performing with more optimal capacitance and device properties than the conventional dual-layer electrode that includes a doped polysilicon layer deposited on a TiN layer.